1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, it relates to a semiconductor device having an SOI structure and a method of fabricating the same.
2. Description of the Background Art
FIG. 29 is a plan view showing the structure of a conventional SOI transistor, FIG. 30 is a sectional view along the line 100xe2x80x94100 in FIG. 29, and FIG. 31 is a sectional view along the line 200xe2x80x94200 in FIG. 29. Referring to FIG. 29 to FIG. 31, a buried oxide film 2 is formed on a silicon substrate 1 in the conventional SOI transistor. A silicon layer 3 is formed on the buried oxide film 2. A gate electrode 12 is provided on the silicon layer 3 through a thin gate insulator film 11. A channel region 15 containing a p-type impurity of about 1xc3x971017/cm3 is formed in a region of the silicon layer 3 under the gate electrode 12. Source/drain regions 14 containing an n-type impurity of about 1xc3x971020/cm3 are formed at a prescribed interval, to hold the channel region 15. Isolation regions 107 containing a p-type impurity of about 1xc3x971018/cm3 which is a higher impurity concentration than the channel region 15 are provided for preventing generation of parasitic MOS transistors on the end portions of the silicon layer 3. In more concrete terms, the end portions of the silicon layer 3 are cut off in ordinary mesa shapes or LOCOS (LOCal Oxidation of Silicon)-isolated. The threshold voltages of these end portions lower since electric fields concentrate or the impurity concentration lowers in such end regions, and the so-called parasitic MOS transistors are generated as a result. In general, therefore, the impurity of a higher impurity concentration than the channel forming region 15 is introduced into the end portions of the silicon layer 3 for increasing the threshold voltages of these portions.
An interlayer isolation film 16 is formed to cover the gate electrode 12, and contact holes 17 are formed in the interlayer isolation film 16 on prescribed regions. Aluminum wires 18 are formed to be connected with the gate electrode 12 and the pair of source/drain regions 14 respectively through the contact holes 17.
With reference to FIG. 32 to FIG. 43, a method of fabricating the conventional SOI transistor is now described. First, holding the buried oxide film 2 having a thickness of about 4000 xc3x85 on the silicon substrate 1, the silicon layer 3 consisting of a single crystal having a thickness of about 1000 xc3x85 is formed thereon, as shown in FIG. 32. The buried oxide film 2 is formed by that high-temperature heat treatment of about 1300xc2x0 C. is performed after oxygen ions are injected into the silicon substrate 1 at 200 keV by about 2xc3x971018/cm2.
Then, a pad oxide film 4 having a thickness of about 300 xc3x85 is formed on the silicon layer 3, and a silicon nitride film 5 having a thickness of about 2000 xc3x85 is formed thereon, as shown in FIG. 33. A photoresist 6 shown in FIG. 34 is formed in a prescribed region on the silicon nitride film 5 with a photolithographic technique. This photoresist 6 has a field active layer pattern. The photoresist 6 is employed as a mask for etching the silicon nitride film 5 and the pad oxide film 4, whereby a silicon nitride film 5 and a pad oxide film 4 of shapes shown in FIG. 35 are formed. Thereafter boron (B) which is a p-type impurity is injected at 20 keV by about 1xc3x971013/cm2, whereby the isolation regions 107 shown in FIG. 36 are formed. Thereafter the photoresist 6 is removed.
Then, a silicon nitride film (not shown) is further deposited on the silicon nitride film 5, and thereafter anisotropic etching is performed thereby forming silicon nitride film spacers 10 shown in FIG. 37 on side walls of the silicon nitride film 5. The silicon nitride film 5 and the silicon nitride film spacers 10 are employed as masks for anisotropically etching the silicon layer 3, whereby an island-shaped silicon layer 3 becoming a field active region shown in FIG. 37 is formed. Thereafter the silicon nitride film 5, the silicon nitride film spacers 10 and the pad oxide film 4 are removed so that a shape shown in FIG. 38 is obtained.
Then, the gate electrode 12 shown in FIG. 39 to FIG. 41 is formed to cover an upper surface and both side surfaces of the silicon layer 3 through the gate insulator film 11. FIG. 39 is a sectional view along a direction where the gate electrode 12 extends, FIG. 40 is a sectional view along a direction orthogonal to FIG. 39, and FIG. 41 is a plan view. A channel dope for adjusting the threshold voltage of the transistor, e.g., boron (B) is injected by about 4xc3x971012/cm2 before formation of the gate electrode 12, thereby forming the channel forming region 15. The gate electrode 12 is patterned as shown in FIG. 39 to FIG. 41, and thereafter the gate electrode 12 is employed as a mask for injecting arsenic (As) which is an n-type impurity by about 1xc3x971015/cm2, as shown in FIG. 42 and FIG. 43. Thus, the n-type source/drain regions 14 holding the channel region 15 are formed. Due to this ion implantation for forming the source/drain regions 14, the (isolation regions 107 into which the p-type impurity is introduced in portions other than that under the gate electrode 12 disappear as shown in FIG. 43.
After the aforementioned formation of the source/drain regions 14, the interlayer isolation film 16 is deposited while the contact holes 17 are opened as shown in FIG. 29 to FIG. 31, and thereafter the aluminum wires 18 are formed. Thus, the conventional SOI transistor has been completed.
In the SOI structure formed by working the semiconductor layer 3 in the aforementioned island shape, crystallinity on end surface portions of the silicon layer 3 deteriorates. Therefore, accelerative diffusion of the impurity from the source/drain regions 14 takes place in the end portions of the silicon layer 3 located under the gate electrode 12, and accelerative diffusion regions 105 shown in FIG. 44 are formed. There has been such a problem that, when such accelerative diffusion regions. 105 are formed, abnormal leakage characteristics shown in FIG. 45 are caused as transistor characteristics.
An object of the present invention is to inhibit accelerative diffusion of an impurity from a source/drain region in a semiconductor device having an SOI structure.
Another object of the present invention is to effectively inhibit generation of abnormal leakage characteristics in a semiconductor device having an SOI structure.
A semiconductor device having an SOI structure according to one aspect of the present invention comprises a semiconductor layer, a pair of source/drain regions of a first conductivity type, and a gate electrode. The semiconductor layer is formed on an insulator and has a major surface. The pair of source/drain regions are formed at an interval to define a channel region on the major surface of the semiconductor substrate. The gate electrode is formed on the major surface of the semiconductor layer through a gate insulator film. Nitrogen is introduced into at least either end portions of the source/drain regions in a direction where the gate electrode extends or an end portion of the semiconductor layer located under the gate electrode. The concentration profile of the nitrogen has a first concentration peak in at least either endmost portions of the source/drain regions in the direction where the gate electrode extends or an endmost portion of the semiconductor layer located under the gate electrode. By thus introducing nitrogen to have a concentration peak in either the endmost portions of the source/drain regions in the direction where the gate electrode extends or the endmost portion of the semiconductor layer located under the gate electrode, the impurity from the source/drain regions is inhibited from diffusing in the endmost portion(s). Consequently, it is possible to effectively inhibit the impurity of the source/drain regions from acceleratively diffusing in the end portion of the semiconductor layer located under the gate electrode. In more concrete terms, point defects or the like serving as mediation for diffusion of the impurity of the source/drain regions are trapped by introduced nitrogen atoms, whereby accelerative diffusion of the impurity from the source/drain regions can be inhibited. Thus, generation of abnormal leakage of transistor characteristics can be prevented.
In the structure of the semiconductor device according to the aforementioned one aspect, a high-concentration impurity region of a second conductivity type may be formed on the end portion of the semiconductor layer located under the gate electrode. When thus structuring the semiconductor device, generation of a parasitic transistor on the end portion of the semiconductor layer located under the gate electrode is inhibited.
In the structure of the semiconductor device according to the aforementioned one aspect, the semiconductor device may be so structured as to plurally form the semiconductor layer in the form of islands at intervals on the insulator.
In the semiconductor device according to the aforementioned one aspect, the semiconductor device is so structured as to separate the semiconductor layer into a plurality of semiconductor layers by an element isolation insulator film formed on the major surface of the semiconductor layer, while introducing nitrogen into a region of the semiconductor layer located in the vicinity of a boundary region between the semiconductor layer and the element isolation insulator film and under the gate electrode, and adjusting the concentration profile of nitrogen to have a concentration peak on an endmost portion of the semiconductor layer which is in contact with the element isolation insulator film. Also when practicing in this way, accelerative diffusion of the impurity from the source/drain regions in the SOI structure isolated by the element isolation insulator film can be prevented.
In the structure of the semiconductor device in the aforementioned one aspect, the semiconductor device is so structured as to introduce nitrogen at least into the source/drain regions, while introducing nitrogen also into the channel region in the vicinity of the source/drain regions. When practicing in this way, the impurity of the source/drain regions can be prevented also from diffusing to the channel region side.
In the structure of the semiconductor device in the aforementioned one aspect, the semiconductor device is so structured as to introduce nitrogen into at least the source/drain regions, while locating a second concentration peak of nitrogen in a vertical direction in the vicinity of an interface between the semiconductor layer and the insulator. By structuring the semiconductor device in this way, diffusion of the impurity from the source/drain regions toward the channel region in the vicinity of the interface between the semiconductor layer and the insulator layer where crystallinity of the semiconductor layer conceivably deteriorates can be effectively prevented.
In a method of fabricating a semiconductor device having an SOI structure in another aspect of the present invention, a semiconductor layer having a major surface is formed on an insulator. A first injection mask is formed on the semiconductor layer. The first injection mask is employed as a mask for injecting a first conductivity type impurity into an isolation injection region of the semiconductor layer thereby forming an impurity region having a higher impurity concentration than a channel region. A gate electrode is formed on the major surface of the semiconductor layer through a gate insulator film. The gate electrode is employed as a mask for ion-implanting a second conductivity type impurity into the semiconductor layer thereby forming a source/drain region. At least either one of the first mask and the gate electrode is employed as a mask for injecting nitrogen. Thereafter heat treatment is performed. By injecting nitrogen and performing heat treatment in this way, the injected nitrogen is piled up on an endmost surface of the semiconductor layer where diffusion of the impurity readily takes place and point defects or the like serving as mediation for diffusion of the impurity of the source/drain region are trapped by nitrogen atoms in this portion, whereby diffusion of the impurity of the source/drain region can be inhibited.
In the method according to the aforementioned other aspect, the method is so structured as to perform injection of nitrogen before ion implantation of the second conductivity type impurity for formation of the source/drain region. Thus, diffusion of the second conductivity type impurity in the source/drain region can be further effectively prevented.
In the aforementioned other method, the method may be so structured as to perform ion implantation of nitrogen so that a second concentration peak of nitrogen in the vertical direction is located in the vicinity of an interface between the semiconductor layer and the insulator by employing the gate electrode as a mask. When practicing in this way, diffusion of the impurity in the vicinity of the interface between the semiconductor layer and the insulator where conceivably a crystal deteriorates and diffusion readily takes place can be further effectively prevented.
In the aforementioned other method, the method may be so structured as to inject nitrogen to a side closer to the channel region than ion implantation of the first conductivity type impurity for forming the source/drain region by employing the gate electrode as a mask. When practicing in this way, it comes to that nitrogen is injected into not only the source/drain region but also the channel region in the vicinity of the source/drain region, and diffusion of the impurity of the source/drain region located in the vicinity of the interface between the source/drain region and the channel region into the channel region can be effectively prevented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.